EPROMs (Electrically Programmable Read Only Memories) are widely used in electronic applications in which low cost, non-volatile memories are desired. Among their many advantages, is their usefulness in applications in which it is desired to have a non-volatile memory capable of being programmed for a specific application, while retaining the flexibility of being able to erase and reprogram that memory.
When it is desired to erase the prior art EPROM, the EPROM is removed from the circuit in which it is employed and then placed in a special erasing apparatus. In this erasing apparatus, the EPROM is exposed to ultraviolet light. The ultraviolet light causes the EPROM to then erase. Once the EPROM is exposed to ultraviolet light in the erasing apparatus, the erase process takes approximately 15-20 minutes in the prior art EPROM. Also, ultraviolet erasable EPROMs must generally be packaged in special, costly ceramic packages containing quartz windows in order for it to be possible to expose the EPROM to ultraviolet light during erasure.
The main disadvantage in using EPROMs is the lack of system flexibility due to the necessity of removing the EPROM from the circuit board in which it is used in order to erase the EPROM. The disadvantage does not exist when EEPROMs (Electrically Erasable Programmable Read Only Memories) are used in place of EPROMs. EEPROMs can be programmed and erased on board, that is, while still in a circuit board. Because of this on-board erasing flexibility, EEPROMs are replacing EPROMs in many applications. However, prior art EEPROMs are much more costly to manufacture than EPROMs. This cost differential between prior art EEPROMs and prior art EPROMs is, for the most part, because the prior art EEPROM cell size is much larger than the EPROM cell size.
A relatively small cell size is typically achieved in prior art ultraviolet erasable EPROMs because these EPROMs use a single transistor per cell. This single transistor cell structure is possible because these EPROMs use hot electron injection mechanisms to program the cells. The EPROM cell is programmed only when both the drain and gate of the cell are raised to a high voltage. Normally, the word line is called the X address and the bit line is called the Y address. This X-Y addressing mode during programming of the cell in an array eliminates the need for byte-select transistors.
Prior art EEPROMs, on the other hand, use Fowler-Nordheim tunneling to program the cells. These prior art EEPROMs require a byte select transistor, as is well known in the art, and the EEPROM requires two transistors per cell. Additionally, as is well known in the art, a tunneling area is needed in each such EEPROM cell. Hence, the prior art EEPROM cell is much larger than the prior art EPROM cell.
Several attempts to overcome the disadvantages of ultraviolet erasable EPROMs have been made. Thus, erasing the EPROMs by tunneling electrons from the floating gate to the control gate through the interpoly oxide has been attempted. Such an attempt is discussed in Guterman, et al., "An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure," IEEE J. SOLID-STATE CIRCUITS, SC-14 p. 498 (April 1979). However, due to the incompatibility between erasability and programming speed, the structure was not successful.
Also, a triple-polysilicon technology employing an erase electrode located between the field oxide and the floating gate has been attempted, as is discussed in Masuoka, et al., "A New Flash E2PROM Cell Using Triple Polysilicon Technology," International Electron Devices Meeting Technical Digest p. 464 (1984). In this technology, the floating gate is erased by Fowler-Nordheim tunneling.
Further, a double polysilicon technology using Fowler-Nordheim tunneling through the dielectric between the floating gate and the drain or source to erase the cells has been attempted, as discussed in Mukherjee, et al., "A Single Transistor EEPROM Cell and its Implementation in a 512K CMOS EEPROM," International Electron Devices Meeting Technical Digest p. 616 (1985). However, all of these attempts to solve the problems inherent in an ultraviolet erasable EPROM share additional problems arising from the overerase of the floating gate that results when these methods to erase an EPROM cell are employed.
When an ultraviolet erasable EPROM is erased, the floating gate is electrically neutral. This is because the ultraviolet light causes "programming" electrons to leave the floating gate, but does not cause the floating gate to acquire a positive charge by causing additional electrons to leave the floating gate. When an EEPROM is erased electrically, through Fowler-Nordheim tunneling or tunneling through the interpoly oxide, the floating gate acquires a positive charge. The result of this positive charge on the floating gate is that the transistor acts like a depletion transistor and therefore leaks current. Hence, false data reads or failures to program can result. It is desired to overcome the problems caused by this overerase phenomenon.
Endurance is another factor in determining whether to employ a prior art EPROM or a prior art EEPROM in a particular application. Endurance is a measure of the number of times that a cell can be erased and rewritten. A part with a high endurance can be erased and rewritten many times, while a part with a low endurance can be erased and rewritten relatively fewer times. Prior art EEPROMs typically have a higher endurance than prior art EPROMs. Thus, although prior art EEPROMs are, typically, more expensive than prior art EPROMS, in applications in which a relatively high endurance and a fast erase are desired, prior art EEPROMs are often used instead of prior art EPROMs.